rUChooses which output to route the input signal to. Connect to a 'List Entry' module.Ctl_LEDBI490BI42BI42020Hx chCUGBI260BI42BI42&0'octave0BI42)0*octave(BI42&0,BI42&0.%$Inverter^BI4910 ch BI3(0pitch0BI4265BI4285BI420:fine0BI42=<fine;5pitch4<0Spare60 pitch select!"BI450SpareIO Mod%(LR"BI4);0SpareIO Mod;X"BI112+7Ceil~B"BI62 CPlugNameable-0.9166BI42IHJ-11 Spare InputH-0.8333BI42LHM-10 Spare InputH-0.75BI42OHP-9 Spare InputH-0.6666BI42RHS-8 Spare InputH-0.5833BI42UHV-7 Spare InputH-0.5BI42XHY-6 Spare InputH-0.4166BI42[H\-5 Spare InputH-0.3333BI42^H_-4 Spare InputH-0.25BI42aHb-3 Spare InputH-0.1666BI42dHe-2 Spare InputH-0.0833BI42gHh-1 Spare InputH0BI42jHk0 Spare InputH0.0833BI42mHn+1 Spare InputH0.1666BI42pHq+2 Spare InputH0.25BI42sHt+3 Spare InputH0.3333BI42vHw+4 Spare InputH0.4166BI42yHz+5 Spare InputH0.5BI42|H}+6 Spare InputH0.5850BI42H+7 Spare InputH0.6666BI42H+8 Spare InputH0.75BI42H+9 Spare InputH0.8333BI42H+10 Spare InputH0.9166BI42H+11 Spare InputH0 Spare Value Fixed ValuesdCSwitchBI399KNQTWZ]`cfilorux{~H Spare InputSwitch (Many->1)JMPSVY\_behknqtwz}*68:J$defaultPatch 1Patch 2Patch 3Patch 4Patch 5Patch 6Patch 7Patch 8Patch 9Patch 10Patch 11Patch 12Patch 13Patch 14Patch 15Patch 16Patch 17Patch 18Patch 19Patch 20Patch 21Patch 22Patch 23Patch 24Patch 25Patch 26Patch 27Patch 28Patch 29Patch 30Patch 31Patch 32Patch 33Patch 34Patch 35Patch 36Patch 37Patch 38Patch 39Patch 40Patch 41Patch 42Patch 43Patch 44Patch 45Patch 46Patch 47Patch 48Patch 49Patch 50Patch 51Patch 52Patch 53Patch 54Patch 55Patch 56Patch 57Patch 58Patch 59Patch 60Patch 61Patch 62Patch 63Patch 64Patch 65Patch 66Patch 67Patch 68Patch 69Patch 70Patch 71Patch 72Patch 73Patch 74Patch 75Patch 76Patch 77Patch 78Patch 79Patch 80Patch 81Patch 82Patch 83Patch 84Patch 85Patch 86Patch 87Patch 88Patch 89Patch 90Patch 91Patch 92Patch 93Patch 94Patch 95Patch 96Patch 97Patch 98Patch 99 Patch 100 Patch 101 Patch 102 Patch 103 Patch 104 Patch 105 Patch 106 Patch 107 Patch 108 Patch 109 Patch 110 Patch 111 Patch 112 Patch 113 Patch 114 Patch 115 Patch 116 Patch 117 Patch 118 Patch 119 Patch 120 Patch 121 Patch 122 Patch 123 Patch 124 Patch 125 Patch 126 Patch 127 Patch 128BI49/10  ct-BI49-00 ch  Ctl_SliderBI5 00-100&-2.51.5 2 0 1octave chlr%BI5 00-100>-0.08330.0833 2 1 1fine.b95rConnection to a module inside'=,.%JpdefaultPatch 1Patch 2Patch 3Patch 4Patch 5Patch 6Patch 7Patch 8Patch 9Patch 10Patch 11Patch 12Patch 13Patch 14Patch 15Patch 16Patch 17Patch 18Patch 19Patch 20Patch 21Patch 22Patch 23Patch 24Patch 25Patch 26Patch 27Patch 28Patch 29Patch 30Patch 31Patch 32Patch 33Patch 34Patch 35Patch 36Patch 37Patch 38Patch 39Patch 40Patch 41Patch 42Patch 43Patch 44Patch 45Patch 46Patch 47Patch 48Patch 49Patch 50Patch 51Patch 52Patch 53Patch 54Patch 55Patch 56Patch 57Patch 58Patch 59Patch 60Patch 61Patch 62Patch 63Patch 64Patch 65Patch 66Patch 67Patch 68Patch 69Patch 70Patch 71Patch 72Patch 73Patch 74Patch 75Patch 76Patch 77Patch 78Patch 79Patch 80Patch 81Patch 82Patch 83Patch 84Patch 85Patch 86Patch 87Patch 88Patch 89Patch 90Patch 91Patch 92Patch 93Patch 94Patch 95Patch 96Patch 97Patch 98Patch 99 Patch 100 Patch 101 Patch 102 Patch 103 Patch 104 Patch 105 Patch 106 Patch 107 Patch 108 Patch 109 Patch 110 Patch 111 Patch 112 Patch 113 Patch 114 Patch 115 Patch 116 Patch 117 Patch 118 Patch 119 Patch 120 Patch 121 Patch 122 Patch 123 Patch 124 Patch 125 Patch 126 Patch 127 Patch 128